The small signal amplification characteristics of the gated diode device structure were originally used to create signal amplifiers and dynamic memory cells, including one transistor one diode (1T1D), two transistor one diode (2T1D), and three transistor one diode (3T1D) memory cells. U.S. patent application Ser. No. 10/735,061, entitled “Gated Diode Memory Cells,” incorporated by reference herein, describes 1T1D and 2T1D gated diode memory cells, a new type of dynamic memory cell with internal voltage amplification based on gated diode circuits and structures. U.S. patent application Ser. No. 10/751,714, entitled “Amplifiers Using Gated Diodes,” incorporated by reference herein, describes gated diode circuits for signal amplification that are suitable for amplifying small amplitude signals. U.S. patent application Ser. No. 10/751,713, entitled “3T1D Memory Cells Using Gated Diodes and Methods of Use Thereof,” incorporated by reference herein, describes dynamic memory cells designed from gated diode circuits.
The gated diode memory cells in the above-identified patent applications are all dynamic designs in that data is retained in the storage node in the form of a unidirectional, single ended voltage and (capacitive) charge. The amount of charge stored eventually decays to a low level due to intrinsic leakage mechanisms, such as transistor off-state current, gate tunneling current, and junction leakage current. The low level charge is insufficient to maintain storage of the data. A “refresh” event is therefore needed (after a certain period of time) to bring the voltage or charge level back to its appropriate level in order to retain the stored data.
These previously proposed memory cells have a number of desirable characteristics, including low voltage operation, high signal to noise ratio, high signal margin, high tolerance to process and threshold voltage (Vt) variations, non-destructive read operation, fast read/write time, and short random access cycle. This allows for the continued scaling of memory for future technologies with lower supply voltages. Due to the signal amplification of the cell voltage of the gated diode memory cells, the memory cells can have a much higher signal margin than existing static random access memory (SRAM), dynamic random access memory (DRAM), and dynamic gain cells.
SRAM has traditionally been used for high performance applications, such as embedded caches in high performance processors, due to its fast read/write times, non-destructive read, short random access cycle, and static data storage (no refresh needed). As technologies are scaled to lower voltages, the static noise margin in the cross-coupled latch in the SRAM cell degrades (i.e., the signal margin or voltage difference between a 0- or 1-voltage and the flip point voltage becomes very small), especially during a read event, in which the internal storage node of the cell is perturbed. With the growing influence of process-induced variations, threshold voltage fluctuations further degrade the SRAM cell stability.
A need therefore exists for a memory device that does not require data refresh, but has the scalability to low voltages, high signal to noise ratio, high signal margin, and tolerance to process variations characteristic of gated diode dynamic memory cells.